Resonance in electrical circuits : Deriving the frequency equation for series resonance

RLC circuit

The current in a series RLC circuit varies with frequency as shown in the graph

I_o is the current at the resonating frequency and I_o/√2 is the current at the lower and higher cut-off frequency and it is 0.707 of I_o value. Lower and higher cut-off frequencies are important because bandwidth is defined in between these frequencies.

Current is calculated as

At critical frequency current is

Combining these two we get

at resonance impedance of the circuit is simply R. Now writing I_o =V/R and substituting value of Z

Cancelling V from both sides and taking reciprocal on both sides

To get rid of j (equivalent i of imaginary number), write the right hand side expression in terms of it's magnitude form

square on both sides 

and simplify

Now square root both sides

Substitute in value for inductive and capacitive impedance in terms of omega,L,C

Further simplify

This is a quadratic equation in ω.

Because of +- sign there are two different quadratic equations. So considering one at a time

Now calculating roots of the above quadratic equation

Now here there are two possible roots. Since frequency cannot be negative so considering positive root.

lets call this ω1 (lower cut-off frequency)

Now considering the second quadratic equation

calculating roots

Now just for observation if you factor out R/4L form inside the squared root, we can see that the term is actually greater than R/2L term, so this term cannot be negative as will make our frequency negative which is fundamentally wrong. 

So choosing the positive root

Lets call this ω2 (higher cut-off frequency)

We can write both the roots together as

Flip-Flops (part 1)

Flip-Flops are basic storage electronic components and are made using gates. Gates are connected in certain configuration which make it capable of maintaining its state. This state then further plays a role in deciding the next output.

Consider a simple AND gate circuit:

 If we set A=1, B=1, C=1 the output Y would equal 1. However the moment we change the inputs to A=0, B=0, C=0 the output Y changes to 0. Now this can be seen as the loss of the i bit information which was present in the circuit.

Now consider the following circuit

For this circuit if you set R=0 and S=1, Q' would be 0 (this is because for a NOR gate if at-least one input is 1 the output is 0). So we can be sure that output Q' is 0.
Now this Q' is fed to the above NOR gate and since R=0 the output Q is 1. You can verify this from below NOR table.

NOR Truth Table

What if you set R=1 and S=0, well its quite intuitive (opposite of R=0 and S=1 condition), and this would set Q=1 and Q' = 0.

Now here comes the interesting part, after setting, R=0 S=1, if you change inputs to S=0 and R=0, the value of Q and Q' does not change! This is because when R is set to 0, Q' which was already 0 (from previous output) and this would give Q =1. Similarly when S=0 and Q=1(from previous output) Q'=0.

Note that Q and Q' are complementary, that is if Q=1 then Q' should be 0.

In the same way you can verify for R=0 S=1 condition. You will find the outputs does not change when you change back to R=0 and S=0.

So we successfully stored our first bit of information in a circuit!
This circuit is called as latch or a Flip-Flop more precisely a SR Flip-Flop, which is one of the types of Flip-Flops.


The following SR-FF truth table summarise the result:

In the table Qn is the value of Q before applying the inputs. Since there is just two possible values Q could take 0 and 1, these combination have been added for every common pair of inputs (S R).

In fact when you power the circuit (by applying power to Vcc of the Flip Flops IC) the circuit would attain either a state with Q=0 (called as reset state) or Q=1 (called as set state). This happen because both the NOR gates have slightly different propagation delay time.

You must have noticed that when inputs S=1 R=1 the output is undetermined this is because when either of the inputs is 1  for a NOR gate it tries to output 1. In this case both Q and Q' would try to attain a 1 state which is not possible (try putting in values of S R and figure out).

So this is all about basics of Flip Flop. In my next post I will talk about a new FF called JK FF which does not get into any problem of undetermined condition.